Computers require significantly more time to execute an instruction which retrieves data from a main memory than to execute an instruction which makes no such storage reference. Storage references can markedly slow the performance of a computer. Accordingly, techniques for eliminating the time penalty for storage references are known to the art. One such technique is to execute instrutions simultaneously with the retrieval of data from memory. Precautions must be taken however to avoid errors caused by a so-called instruction dependency where execution of an instruction changes the contents of a memory location, but, before the change is effected, data is retrieved from that location for use by a subsequent instruction. In this case, the first instruction must be allowed to complete execution before retrieval of the data by the subsequent instruction.
Provision of simultaneous storage data references and instruction execution is particularly desirable in a reduced instruction-set computer (RISC) since one object of such computers is improved execution times. However, RISC's pose two problems for the application of prior art techniques such as mentioned above. First, a RISC usually includes a relatively large general purpose file register for the storage of often-used data. It is desirable to provide a separate data path from main memory into each register of the file so that data retrieved from storage may be written to any register within the file at the same time that data which results from the execution of an instruction is written to the file. Any delay in the writing is undesirable as it undermines the time improvement realized by the simultaneous data reference and instruction execution. The relatively large number of registers in a RISC file register makes the implementation of the separate data path uneconomical.
Secondly, RISC's omit the microcode level of procesor control. Since the availability of microcode programming is often used to handle memory page faults through an interrupt procedure, RISC's must provide alternatives in both hardware and the software at the instruction set level to meet demand paging requirements.